Shared context, separate engines: letting an NPU prefetch while a GPU decodes on the same streaming request
AspireAI community · arXiv
Edge SoCs combine CPUs, GPUs and NPUs, but multimodal LLM runtimes keep generation on a single engine and leave the others idle, and backend-local KV state binds a query to whichever engine built its history. This system separates logical history from engine-specific KV state so any language engine can continue a stream, with stateful streaming generation overlapping ingestion and answering, concurrent sequence generation serving ready queries in parallel, and phase-level state continuation letting one engine prefill a query while another decodes the answer so the first can resume ingestion. A state-driven execution planner chooses paths by predicted completion time and assigns each engine's share of queries from arrival rates and measured service times. Across M4 Max, RK3588 and QCS6490 it beats the strongest single-engine baselines, cutting live-stream p95 time to first token by 76 percent on M4 Max with every first token inside one second, and raising backlog throughput by up to 35 percent.
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Two sparse-autoencoder analyses have resisted scaling: matching semantically similar features across layers, and compressing large feature circuits into interpretable supernodes. This paper argues both are the same underlying problem, estimating semantic distances between SAE features that sit on different activation manifolds. Its representation treats each feature not as a single decoder vector but as an activation-weighted distribution over the hidden states expressing it, projects those distributions into a shared reference space, and compares them with Wasserstein distance. The representation is proved invariant to activation rescaling and stable under perturbation, and recovers true matches under finite-sample margin conditions. Empirically it outperformed decoder-vector and LLM-based baselines and captured subtle functional distinctions between related features, and it compressed large feature circuits into interpretable supernodes automatically. The limitation is that this is interpretability tooling: the paper demonstrates better feature matching and circuit compression, not that downstream interpretability claims become more accurate.