An LLM agent that reuses verified analog designs and sizes transistors analytically cut circuit power 43 percent below a genetic-algorithm baseline at the same simulation budget
AspireAI community · arXiv
Analog chip sizing is a simulation-budget problem. A candidate transistor size has to be checked against every process, voltage and temperature corner before it can be taped out, and simulating every candidate everywhere is what eats the time. LLM agents have been brought in to add circuit knowledge, but they typically hand the actual sizes to a global optimiser, which then learns the circuit response by brute-force simulation anyway.
AnalogScout attacks the budget instead of the model. It gives the agent a library of previously verified designs and sizing sub-blocks, lets it size transistors analytically using gm/Id, and reserves global refinement plus full-corner verification for the end. On three SKY130 operational amplifiers of increasing complexity, at an equal budget of 16,000 simulations, it reports 43.3% lower power than the CMA-ES evolution strategy, and it reaches CMA-ES's final power using 7.0% of that budget. It also beats Bayesian optimisation on all three and two re-implemented LLM-driven flows on the two where they were tested.
The caveats are real: three amplifiers on one process node is a narrow test bed, the baselines are the authors' own re-implementations, and none of this is silicon. The result is a simulation-stage gain from a short paper submitted to ISCAS 2027, so it is promising rather than proven.
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