Serving runtimes normally leave the CPU waiting on the GPU, so this one gave the host its own scheduler
AspireAI community · arXiv
When an LLM serving runtime offloads part of the KV cache to host memory, CPU-resident requests generally only make progress when the GPU scheduler happens to expose an overlap opportunity, which produces bursty CPU-side progress and inflated tail inter-token latency. DualPace splits scheduling authority across two engines: the GPU engine handles prefills and GPU-resident decodes, while an AMX-enabled CPU engine independently batches and advances the requests living in host memory, with the CPU able to run a full decode iteration locally or call back to the GPU for dense stages. In decode-oriented scenarios the authors report throughput gains of 6.9% to 43.2% over NEO and 11.5% to 90.6% over vLLM at the same latency level, while keeping NEO's P99 time-to-first-token advantage and sustaining 7.3% to 50.5% higher request rates at equal P99 inter-token latency. The gains depend on an AMX-capable host CPU.
Read the story and explore more from the AspireAI community.
Two sparse-autoencoder analyses have resisted scaling: matching semantically similar features across layers, and compressing large feature circuits into interpretable supernodes. This paper argues both are the same underlying problem, estimating semantic distances between SAE features that sit on different activation manifolds. Its representation treats each feature not as a single decoder vector but as an activation-weighted distribution over the hidden states expressing it, projects those distributions into a shared reference space, and compares them with Wasserstein distance. The representation is proved invariant to activation rescaling and stable under perturbation, and recovers true matches under finite-sample margin conditions. Empirically it outperformed decoder-vector and LLM-based baselines and captured subtle functional distinctions between related features, and it compressed large feature circuits into interpretable supernodes automatically. The limitation is that this is interpretability tooling: the paper demonstrates better feature matching and circuit compression, not that downstream interpretability claims become more accurate.