Layout conversion was eating 6.4% of training step time: zero-copy FSDP collectives cut it up to 27%
AspireAI community · arXiv (TIDE)
TIDE folds FSDP2 layout placement into collective addressing instead of copying all-gather output into parameter storage and packing gradients into full-group fp32 buffers, using NVSwitch multicast and paced recursive-doubling RDMA for shards, plus copy engines and short-lived CTAs for node-local accumulation in a mixed-precision reduce-scatter NCCL does not offer. On 64 GPUs it reduces step time by up to 27.1% against stock FSDP2 and 6.0% against FSDP2+SymmMem across Llama-3.1 70B, Wan2.2 and Qwen3-30B-A3B, cuts reduce-scatter SM time by factors of 12.5 to 14.5, and keeps its buffer nearly constant from 16 to 64 GPUs. The measurements come from one NVSwitch and RDMA cluster configuration.
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Two sparse-autoencoder analyses have resisted scaling: matching semantically similar features across layers, and compressing large feature circuits into interpretable supernodes. This paper argues both are the same underlying problem, estimating semantic distances between SAE features that sit on different activation manifolds. Its representation treats each feature not as a single decoder vector but as an activation-weighted distribution over the hidden states expressing it, projects those distributions into a shared reference space, and compares them with Wasserstein distance. The representation is proved invariant to activation rescaling and stable under perturbation, and recovers true matches under finite-sample margin conditions. Empirically it outperformed decoder-vector and LLM-based baselines and captured subtle functional distinctions between related features, and it compressed large feature circuits into interpretable supernodes automatically. The limitation is that this is interpretability tooling: the paper demonstrates better feature matching and circuit compression, not that downstream interpretability claims become more accurate.