aspireai.
PUBLIC EDITION

Chip evaluation, not simulation: LLM agents designed a three-wide out-of-order RISC-V core on an FPGA

AspireAI community · arXiv (kadomoto-lab)
A development environment puts LLM agents in a loop where they implement CPU candidates, lint them, and read on-board FPGA measurements to decide what to try next, replacing long RTL simulation runs with real hardware feedback. Applied to human-supervised development from a single-cycle RV32I core to a three-wide out-of-order RV32IM core, the final design reaches 5.61 CoreMark/MHz at 130 MHz on an Artix-7 FPGA, and evaluating one candidate over 8,000 CoreMark iterations was 9.6x faster than single-threaded RTL simulation. In one case board measurements revealed long-run degradation in a candidate that looked good in a short diagnostic run, which redirected the work to an RTL-level root-cause fix; the work is submitted to IEEE ISCAS 2027 and the human supervision remains a real part of the loop.
Read the story and explore more from the AspireAI community.
Discover more stories
Stay curious.
THE BIG PICTURE
A FRESH PERSPECTIVE
Research
One distance function matched sparse-autoencoder features across layers and compressed feature circuits into supernodes
Two sparse-autoencoder analyses have resisted scaling: matching semantically similar features across layers, and compressing large feature circuits into interpretable supernodes. This paper argues both are the same underlying problem, estimating semantic distances between SAE features that sit on different activation manifolds. Its representation treats each feature not as a single decoder vector but as an activation-weighted distribution over the hidden states expressing it, projects those distributions into a shared reference space, and compares them with Wasserstein distance. The representation is proved invariant to activation rescaling and stable under perturbation, and recovers true matches under finite-sample margin conditions. Empirically it outperformed decoder-vector and LLM-based baselines and captured subtle functional distinctions between related features, and it compressed large feature circuits into interpretable supernodes automatically. The limitation is that this is interpretability tooling: the paper demonstrates better feature matching and circuit compression, not that downstream interpretability claims become more accurate.
Swipe into something new
01 / 1729
The conversation continues
Explore Builds — projects by Kiran Adimatyam ↗
A fresh perspective changes everything.
ASPIREAI — STAY CURIOUS.