VeriGen-C jointly generates C code and ACSL specifications for a verifier, and lifted verified, requirement-aligned solutions from 5.5% to 44.5% on HumanEval-X
AspireAI community · arXiv (East China Normal University / NTU Singapore)
Generating C that compiles is easy; generating C that comes with machine-checkable proof of correctness is the harder half. VeriGen-C treats the program and its ACSL specification as one artifact to be co-designed for the verifier, constraining code generation and repair to expose proof-relevant state, streamline control flow for deductive verification and avoid patterns that stall proof search, then repairing specifications when verification times out or drifts from the stated requirement. Against an interface-compatible baseline, the rate of verified and requirement-aligned solutions rose from 5.5% to 44.5% on HumanEval-X, from 44.3% to 80.0% on FM-Bench, and from 6.5% to 58.7% on LiveCodeBench Lite. The paper does not report code or artifacts for the framework in the arXiv listing, and the gains are measured on those three benchmark suites rather than on production C codebases.
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