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EdgeCIM: A Hardware-Software Co-Design for CIM-Based Acceleration of Small Language Models

AspireAI community · arXiv
EdgeCIM is a hardware-software co-design for autoregressive decoding of small language models on edge devices, built around a compute-in-memory macro implemented in 65 nm with a tile-based mapping strategy that balances pipeline stages to relieve DRAM bandwidth bottlenecks. The authors use a simulator for design-space exploration up to 4B parameters and report that on LLaMA3.2 3B at INT4 it achieves 1.76x and 3.21x higher throughput than NVIDIA Jetson AGX Orin and Orin Nano Super in MAXN mode, and 7.07x higher than Qualcomm's Snapdragon-X Elite. Across a wider benchmark set including TinyLLaMA, LLaMA3.2, Phi 3.5 mini, Qwen2.5, SmolLM2, SmolLM3 and Qwen3 variants, they report an average of 336.4 tokens/s and 173 tokens/J at INT4. These are simulation results rather than silicon, and the work was accepted at IEEE TCAD.
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One distance function matched sparse-autoencoder features across layers and compressed feature circuits into supernodes
Two sparse-autoencoder analyses have resisted scaling: matching semantically similar features across layers, and compressing large feature circuits into interpretable supernodes. This paper argues both are the same underlying problem, estimating semantic distances between SAE features that sit on different activation manifolds. Its representation treats each feature not as a single decoder vector but as an activation-weighted distribution over the hidden states expressing it, projects those distributions into a shared reference space, and compares them with Wasserstein distance. The representation is proved invariant to activation rescaling and stable under perturbation, and recovers true matches under finite-sample margin conditions. Empirically it outperformed decoder-vector and LLM-based baselines and captured subtle functional distinctions between related features, and it compressed large feature circuits into interpretable supernodes automatically. The limitation is that this is interpretability tooling: the paper demonstrates better feature matching and circuit compression, not that downstream interpretability claims become more accurate.
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