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An LLM repaired up to 98 percent of single-line and 93 percent of multi-line RTL bugs, with every patch checked by a model checker

AspireAI community · arXiv preprint
Most LLM-assisted hardware-debugging work stops at a plausible patch. This work closes that loop: the model proposes a fix, and a formal model checker decides whether the patch is allowed to stand. The method guides the LLM with failing assertions, then verifies every candidate patch with JasperGold before accepting it, so an incorrect patch is rejected rather than shipped. Evaluated on the BRISC-V RISC-V core using mutation testing across several mutation types, the methodology repairs up to 98% of single-line RTL bugs and 93% of multi-line bugs - the multi-line case being the hard one, since a single mutation often spans several lines and needs different fixes in different places. The practical claim is that formal verification can act as a filter around a generative model instead of the model being trusted on its own, which is a different architecture from most LLM-for-RTL tools. Caveat: the bugs are injected mutations on one RISC-V core rather than real silicon defects, and the 98% and 93% are the authors' upper-bound figures.
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